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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Figure 3. Transactions on the SPI-3 Transmit Interface
TFCLK
TENB
TSOP
TEOP
TMOD[1:0]
TERR
TSX
Bridge Core User’s Guide
TDAT[31:0]
0000
B1-B4
B5-B8
B41-B44 B45-B48 B49-B52
B53-B56
B57
0001
B1-B4
TPRTY
STPA
DTPA[0]
DTPA[1]
Figure 4 shows the use of the polling feature of the transmit interface. For comparison purposes, the “direct trans-
mit packet available” signals for the example ports are provided in the diagram. The status of a given PHY port may
be determined by setting the polling address TADR bus to the port address. The “polled transmit packet available”
signal PTPA is updated with the transmit FIFO status in a pipelined manner. The Link Layer device is not restricted
in its polling order. The “selected transmit packet available” STPA signal allows monitoring of the selected PHY sta-
tus and halting of the data transfer once the FIFO is full. The PTPA signal allows polling other PHY’s at any time,
including while a data transfer is in progress.
Figure 4. Packet Level Transmit Polling
TFCLK
TADR[n:0]
P0
P1
P2
P3
P0
P1
P2
P0
P1
P2
P3
PTPA
P0
P1
P2
P3
P3
P0
P1
P2
P0
P1
P2
P3
DTPA[0]
DTPA[1]
DTPA[2]
DTPA[3]
Transmit Interface AC Timing
Table 6. Transmit Interface Timing
Symbol
tS tenb
tH tenb
tS tdat
tH tdat
tS tprty
tH tprty
tS tsop
tH tsop
tS teop
tH teop
tS tmod
tH tmod
Description
TFCLK Frequency
TFCLK Duty Cycle
TENB Set-up time to TFCLK
TENB Hold time to TFCLK
TDAT[15:0] Set-up time to TFCLK
TDAT[15:0] Hold time to TFCLK
TDPRTY Set-up time to TFCLK
TDPRTY Hold time to TFCLK
TSOP Set-up time to TFCLK
TSOP Hold time to TFCLK
TEOP Set-up time to TFCLK
TEOP Hold time to TFCLK
TMOD Set-up time to TFCLK
TMOD Hold time to TFCLK
Min.
—
40
2
0.5
2
0.5
2
0.5
2
0.5
2
0.5
2
0.5
Max.
104
60
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
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